View CY7C1463AV25_8442506.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

preliminary 36-mbit (1m x 36/2m x 18/ 512k x 72) flow-through sram with nobl? architecture cy7c1461av25 CY7C1463AV25 cy7c1465av25 cypress semiconductor corporation ? 3901 north first street ? san jose , ca 95134 ? 408-943-2600 document #: 38-05355 rev. *b revised february 9, 2005 features ? no bus latency? (nobl?) architecture eliminates dead cycles between write and read cycles ? can support up to 133-mhz bus operations with zero wait states ? data is transferred on every clock ? pin-compatible and functionally equivalent to zbt? devices ? internally self-time d output buffer cont rol to eliminate the need to use oe ? registered inputs for flow-through operation ? byte write capability ? 2.5v/1.8v i/o power supply ? fast clock-to-output times ? 6.5 ns (for 133-mhz device) ? 8.5 ns (for 100-mhz device) ? clock enable (cen ) pin to enable clock and suspend operation ? synchronous self-timed writes ? asynchronous output enable ? offered in jedec-standard lead-free 100 tqfp and 165-ball fbga packages and 209-ball fbga package ? three chip enables for simple depth expansion ? automatic power-down feature available using zz mode or ce deselect ? jtag boundary scan for bga and fbga packages ? burst capability?linear or interleaved burst order ? low standby power functional description [1] the cy7c1461av25/CY7C1463AV25/cy7c1465av25 are 2.5v, 1-mbit 36/2-mbit 18/512k 72 synchronous flow- through burst srams designed spec ifically to support unlimited true back-to-back read/write operations without the insertion of wait states. the cy7c1461av25/CY7C1463AV25/ cy7c1465av25 is equipped with the advanced no bus latency (nobl) logic required to enable consecutive read/write operations with dat a being transferred on every clock cycle. this feature dramatically improves the throughput of data through the sram, especially in systems that require frequent write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock input is qualified by the clock enable (cen ) signal, which when deasserted suspends operation and extends the previous clock cycle. maximum access delay from the clock rise is 6.5 ns (133-mhz device). write operations are controlled by the two or four byte write select (bw x ) and a write enable (we ) input. all writes are conducted with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) provide for easy bank selection and output tri-state control. in order to avoid bus contention, the output driver s are synchronously tri-stated during the data portion of a write sequence. selection guide 133 mhz 100 mhz unit maximum access time 6.5 8.5 ns maximum operating current 270 250 ma maximum cmos standby current 100 100 ma shaded areas contain advance information. note: 1. for best-practices recommendations, please refer to the cypress application note system design guidelines on www.cypress.com.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 2 of 28 1 c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b dqp c dqp d memory array e input register bw c bw d address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control logic block diagram ? cy7c1461av25 (1 mbit 36) logic block diagram ? CY7C1463AV25 (2 mbit 18) c mode bw a bw b we ce1 ce2 ce3 oe read logic dqs dqp a dqp b memory array e input register address register write registry and data coherency control logic burst logic a0' a1' d1 d0 q1 q0 a0 a1 adv/ld ce adv/ld c c lk c en write drivers d a t a s t e e r i n g s e n s e a m p s write address register a0, a1, a o u t p u t b u f f e r s e zz sleep control
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 3 of 28 2 logic block diagram ? cy7c1465av25 (512k 72) a0, a1, a c mode ce1 ce2 ce3 oe read logic dq s dq p a dq p b dq p c dq p d dq p e dq p f dq p g dq p h d a t a s t e e r i n g o u t p u t b u f f e r s memory array e e input register 0 address register 0 write address register 1 write address register 2 burst logic a0' a1' d1 d0 q1 q0 a0 a1 c adv/ld adv/ld e input register 1 s e n s e a m p s o u t p u t r e g i s t e r s e c lk c en write drivers bw a bw b we zz sleep control bw c write registry and data coherency control logic bw d bw e bw f bw g bw h
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 4 of 28 pin configurations 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd a a a a a a dqp b dq b dq b v ddq v ss dq b dq b dq b dq b v ss v ddq dq b dq b v ss nc v dd dq a dq a v ddq v ss dq a dq a dq a dq a v ss v ddq dq a dq a dqp a dqp c dq c dq c v ddq v ss dq c dq c dq c dq c v ss v ddq dq c dq c nc v dd nc v ss dq d dq d v ddq v ss dq d dq d dq d dq d v ss v ddq dq d dq d dqp d a a ce 1 ce 2 bw d bw c bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc / 72m cy7c1461av25 byte a byte b byte d byte c a a
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 5 of 28 pin configurations (continued) 100-lead tqfp a a a a a1 a0 nc / 288m nc / 144m v ss v dd a a a a a a a nc nc v ddq v ss nc dqp a dq a dq a v ss v ddq dq a dq a v ss nc v dd dq a dq a v ddq v ss dq a dq a nc nc v ss v ddq nc nc nc nc nc nc v ddq v ss nc nc dq b dq b v ss v ddq dq b dq b nc v dd nc v ss dq b dq b v ddq v ss dq b dq b dqp b nc v ss v ddq nc nc nc a a ce 1 ce 2 nc nc bw b bw a ce 3 v dd v ss clk we cen oe a a 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 a a adv/ld zz mode nc / 72m CY7C1463AV25 byte a byte b a a
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 6 of 28 pin configurations (continued) 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc dqp c dq c dqp d nc dq d a ce 1 bw b ce 3 bw c cen a ce2 dq c dq d dq d mode nc dq c dq c dq d dq d dq d nc/72m v ddq bw d bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq c v ss dq c v ss dq c dq c nc v ss v ss v ss v ss nc v ss a1 dq d dq d nc nc v ddq v ss tms 891011 nc a a adv/ld nc oe a a nc/144m v ss v ddq nc dqp b v ddq v dd dq b dq b dq b nc dq b nc dq a dq a v dd v ddq v dd v ddq dq b v dd nc v dd dq a v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq dq a v ddq a a v ss a a a dq b dq b dq b zz dq a dq a dqp a dq a a v ddq a 234 567 1 a b c d e f g h j k l m n p r tdo nc/288m nc nc nc dqp b nc dq b a ce 1 ce 3 bw b cen a ce2 nc dq b dq b mode nc dq b dq b nc nc nc nc/72m v ddq bw a clk we v ss v ss v ss v ss v ddq v ss v dd v ss v ss v ss nc v ss v ss v ss v ss v ddq v ddq nc v ddq v ddq v ddq v ddq a a v dd v ss v dd v ss v ss v ddq v dd v ss v dd v ss v dd v ss v ss v ss v dd v dd v ss v dd v ss v ss nc tck a0 v ss tdi a a dq b v ss nc v ss dq b nc nc v ss v ss v ss v ss nc v ss a1 dq b nc nc nc v ddq v ss tms 891011 nc a a adv/ld nc/144m a oe a a v ss v ddq nc dqp a v ddq v dd nc dq a dq a nc nc nc dq a nc v dd v ddq v dd v ddq dq a v dd nc v dd nc v dd v ddq dq a v ddq v dd v dd v ddq v dd v ddq nc v ddq a a v ss a a a dq a nc nc zz dq a nc nc dq a a v ddq a CY7C1463AV25 (2 mbit 18) cy7c1461av25 (1 mbit 36) 165-ball fbga pinout a a nc nc
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 7 of 28 pin configurations (continued) a b c d e f g h j k l m n p r t u v w 123456789 11 10 dqg dqg dqg dqg dqg dqg dqg dqg dqc dqc dqc dqc nc dqpg dqh dqh dqh dqh dqd dqd dqd dqd dqpd dqpc dqc dqc dqc dqc nc dqh dqh dqh dqh dqph dqd dqd dqd dqd dqb dqb dqb dqb dqb dqb dqb dqb dqf dqf dqf dqf nc dqpf dqa dqa dqa dqa dqe dqe dqe dqe dqpa dqpb dqf dqf dqf dqf nc dqa dqa dqa dqa dqpe dqe dqe dqe dqe aa aa nc nc nc nc/72m a nc a aa aa a a1 a0 a aa aa a nc nc nc nc nc nc bws b bws f bws e bws a bws c bws g bws d bws h tms tdi tdo tck nc nc mode nc cen v ss nc clk nc v ss v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v dd v ss v ss v ss v ss v ss v ss v ss v ss nc v dd nc oe ce 3 ce 1 ce 2 adv/ld we v ss v ss v ss v ss v ss v ss v ss zz v ss v ss v ss v ss nc v ddq v ss v ss nc v ss v ss v ss v ss v ss v ss nc v ss v ddq v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq nc v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq v ddq 209-ball pbga cy7c1465av25 (512k 72) pin definitions pin name i/o type pin description a0 a1 a input- synchronous address inputs used to select one of the address locations . sampled at the rising edge of the clk. bw a bw b bw c bw d bw e bw f bw g bw h input- synchronous byte write select inputs, active low . qualified with we to conduct writes to the sram. sampled on the rising edge of clk. bw a controls dq a and dqp a , bw b controls dq b and dqp b , bw c controls dq c and dqp c , bw d controls dq d and dqp d , bw e controls dq e and dqp e , bw f controls dq f and dqp f , bw g controls dq g and dqp g , bw h controls dq h and dqp h . we input- synchronous write enable input, active low . sampled on the rising edge of clk if cen is active low. this signal must be asserted low to initiate a write sequence. adv/ld input- synchronous advance/load input used to advance the on-chip address counter or load a new address . when high (and cen is asserted low) the internal burst counter is advanced. when low, a new address can be loaded into the device for an access. after being deselected, adv/ld should be driven low in order to load a new address.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 8 of 28 clk input- clock clock input . used to capture all synchronous inputs to the device. clk is qualified with cen . clk is only recognized if cen is active low. ce 1 input- synchronous chip enable 1 input, active low . sampled on the rising edge of clk. used in conjunction with ce 2 and ce 3 to select/deselect the device. ce 2 input- synchronous chip enable 2 input, active high . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 3 to select/deselect the device. ce 3 input- synchronous chip enable 3 input, active low . sampled on the rising edge of clk. used in conjunction with ce 1 and ce 2 to select/deselect the device. oe input- asynchronous output enable, active low . combined with the synchronous logic block inside the device to control the direction of the i/o pins. when low, t he i/o pins are allowed to behave as outputs. when deasserted high, i/o pins are tri-stated, and act as input data pins. oe is masked during the data portion of a write sequence, during the fi rst clock when emerging from a deselected state and when the device has been deselected. cen input- synchronous clock enable input, active low . when asserted low the clock signal is recognized by the sram. when deasserted high the clock signal is masked. since deasserting cen does not deselect the device, cen can be used to extend th e previous cycle when required. dq a dq b dq c dq d dq e dq f dq g dq h i/o- synchronous bidirectional data i/o lines . as inputs, they feed into an on-chip data register that is triggered by the rising edge of clk. as outputs, they deliver the data contained in the memory location specified by a x during the previous clock rise of the read cycle. the direction of the pins is controlled by oe and the internal control logic. when oe is asserted low, the pins can behave as outputs. when high, dq a ?dq d are placed in a tri-state cond ition. the outputs are automat- ically tri-stated during the data portion of a writ e sequence, during the first clock when emerging from a deselected state, and when the device is deselected, regardless of the state of oe . dqp a dqp b dqp c dqp d dqp e dqp f dqp g dqp h i/o- synchronous bidirectional data parity i/o lines . functionally, these signals are identical to dq [31:0] . during write sequences, dqp a is controlled by bw a , dqp b is controlled by bw b , dqp c is controlled by bw c , and dqp d is controlled by bw d , dqp e is controlled by bw e , dqp f is controlled by bw f , dqp g is controlled by bw g , dqp h is controlled by bw h . mode input strap pin mode input . selects the burst order of the device. tied high selects the interleaved burst order. pulled low selects the linear burst order. mode should not change states during operation. when left floating mode will default high, to an interleaved burst order. tdo jtag serial output synchronous serial data-out to the jtag circuit . delivers data on the negative edge of tck. tdi jtag serial input synchronous serial data-in to the jtag circuit . sampled on the rising edge of tck. tms test mode select synchronous this pin controls the test access port state machine . sampled on the rising edge of tck. tck jtag-clock clock input to th e jtag circuitry . v dd power supply power supply inputs to the core of the device . v ddq i/o power supply power supply for the i/o circuitry . v ss ground ground for the device . should be connected to ground of the system. nc n/a no connects . this pin is not connected to the die. nc/72m n/a not connected to the die . can be tied to any voltage level. nc /144m n/a not connected to the die . can be tied to any voltage level. nc /288m n/a not connected to the die . can be tied to any voltage level. zz input- asynchronous zz ?sleep? input . this active high input places the devic e in a non-time critical ?sleep? condition with data integrity preserved. during normal op eration, this pin can be connected to v ss or left floating. pin definitions (continued) pin name i/o type pin description
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 9 of 28 functional overview the cy7c1461av25/CY7C1463AV25/cy7c1465av25 is a synchronous flow-through burst sram designed specifically to eliminate wait states dur ing write-read transitions. all synchronous inputs pass through input registers controlled by the rising edge of the clock. the clock signal is qualified with the clock enable input signal (cen ). if cen is high, the clock signal is not recognized and all internal states are maintained. all synchronous operations are qualified with cen . maximum access delay from the clock rise (t cdv ) is 6.5 ns (133-mhz device). accesses can be initiated by asserting all three chip enables (ce 1 , ce 2 , ce 3 ) active at the rising edge of the clock. if clock enable (cen ) is active low and adv/ld is asserted low, the address presented to the device will be latched. the access can either be a read or write operation, depending on the status of the write enable (we ). bw x can be used to conduct byte write operations. write operations are qualified by the write enable (we ). all writes are simplified with on-chip synchronous self-timed write circuitry. three synchronous chip enables (ce 1 , ce 2 , ce 3 ) and an asynchronous output enable (oe ) simplify depth expansion. all operations (reads, writes, and deselects) are pipelined. adv/ld should be driven low once the device has been deselected in order to load a new address for the next operation. single read accesses a read access is initiated when the following conditions are satisfied at clo ck rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, (3) the write enable input signal we is deasserted high, and (4) adv/ld is asserted low. the address presented to the address inputs is latched into the address register and presented to the memory array and control logic. the control logic determines that a read access is in progress and allows the requested data to propagate to the output buffers. the data is available within 6.5 ns (133-mhz device) provided oe is active low. after the first clock of the read access, the output buffers are controlled by oe and the internal control logic. oe must be driven low in order for the device to drive out the requested data. on the subsequent clock, another oper ation (read/write/deselect) can be initiated. when the sram is deselected at clock rise by one of the chip enable signals, its output will be tri-stated immediately. burst read accesses the cy7c1461av25/CY7C1463AV25/cy7c1465av25 has an on-chip burst count er that allows th e user the ability to supply a single address and conduct up to four reads without reasserting the address inputs. adv/ld must be driven low in order to load a new address into the sram, as described in the single read access section above. the sequence of the burst counter is determined by the mode input signal. a low input on mode selects a linear burst mode, a high selects an interleaved burst sequence. both burst counters use a0 and a1 in the burst sequence, and will wrap around when incre- mented sufficiently. a high input on adv/ld will increment the internal burst counter regard less of the state of chip enable inputs or we . we is latched at the beginning of a burst cycle. therefore, the type of access (read or write) is maintained throughout the burst sequence. single write accesses write access are initiated w hen the following conditions are satisfied at clock rise: (1) cen is asserted low, (2) ce 1 , ce 2 , and ce 3 are all asserted active, and (3) the write signal we is asserted low. the address presented to the address bus is loaded into the address register. the write signals are latched into the control logic block. the data lines are automatically tri-stated regar dless of the state of the oe input signal. this allows the external logic to present the data on dq s and dqp x . on the next clock rise the data presented to dq s and dqp x (or a subset for byte write o perations, see truth table for details) inputs is latched into the device and the write is complete. additional accesses (read/write/deselect) can be initiated on this cycle. the data written during the write operation is controlled by bw x signals. the cy7c1461av25/CY7C1463AV25/cy7c1465av25 provides byte write capability that is described in the truth table. asserting the write enable input (we ) with the selected byte write select input will selectively write to only the desired bytes. bytes not selected during a byte write operation will remain unaltered. a synchronou s self-timed wr ite mechanism has been provided to simplify the write operations. byte write capability has been included in order to greatly simplify read/modify/write sequences, which can be reduced to simple byte write operations. because the cy7c1461av25/CY7C1463AV25/cy7c1465av25 is a common i/o device, data should not be driven into the device while the outputs are active. the output enable (oe ) can be deasserted high before presenting data to the dqs and dqp x inputs. doing so will tri-state the output drivers. as a safety precaution, dqs and dqp x are automatically tri-stated during the data porti on of a write cycle, regardless of the state of oe . burst write accesses the cy7c1461av25/CY7C1463AV25/cy7c1465av25 has an on-chip burst counter that allows the user the ability to supply a single address and conduct up to four write opera- tions without reasserting the address inputs. adv/ld must be driven low in order to load t he initial address, as described in the single write access section above. when adv/ld is driven high on the subsequent clock rise, the chip enables (ce 1 , ce 2 , and ce 3 ) and we inputs are ignored and the burst counter is incremented. the correct bw x inputs must be driven in each cycle of the burs t write, in order to write the correct bytes of data.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 10 of 28 sleep mode the zz input pin is an asynchronous input. asserting zz places the sram in a power conservation ?sleep? mode. two clock cycles are required to enter into or exit from this ?sleep? mode. while in this mode, data integrity is guaranteed. accesses pending when entering the ?sleep? mode are not considered valid nor is the completion of the operation guaranteed. the device must be deselected prior to entering the ?sleep? mode. ce 1 , ce 2 , and ce 3 , must remain inactive for the duration of t zzrec after the zz input returns low. interleaved burst address table (mode = floating or v dd ) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 00 11 10 10 11 00 01 11 10 01 00 linear burst address table (mode = gnd) first address a1: a0 second address a1: a0 third address a1: a0 fourth address a1: a0 00 01 10 11 01 10 11 00 10 11 00 01 11 00 01 10 zz mode electrical characteristics parameter description test conditions min. max. unit i ddzz sleep mode standby current zz > v dd ? 0.2v tbd ma t zzs device operation to zz zz > v dd ? 0.2v 2t cyc ns t zzrec zz recovery time zz < 0.2v 2t cyc ns t zzi zz active to sleep current t his parameter is sampled 2t cyc ns t rzzi zz inactive to exit sleep current this parameter is sampled 0 ns truth table [2, 3, 4, 5, 6, 7, 8] operation address used ce 1 ce 2 ce 3 zz adv/ld we bw x oe cen clk dq deselect cycle none h x x l l x x x l l->h tri-state deselect cycle none x x h l l x x x l l->h tri-state deselect cycle none x l x l l x x x l l->h tri-state continue deselect cycle none x x x l h x x x l l->h tri-state read cycle (begin burst) external l h l l l h x l l l->h data out (q) read cycle (continue burst) next x x x l h x x l l l->h data out (q) nop/dummy read (begin burst) external l h l l l h x h l l->h tri-state dummy read (continue burst) next xxxl h xxhll->htri-state write cycle (begin burst) external l h l l l l l x l l->h data in (d) write cycle (continue burst) next x x x l h x l x l l->h data in (d) nop/write abort (begin burst) none l h l l l l h x l l->h tri-state write abort (continue burst) next x x x l h x h x l l->h tri-state ignore clock edge (stall) current x x x l x x x x h l->h ? sleep mode none x x x h x x x x x x tri-state notes: 2. x = ?don't care.? h = logic high, l = logic low. bw x = l signifies at least one by te write select is active, bw x = valid signifies that the desired byte write selects are asserted, see truth table for details. 3. write is defined by bw x , and we . see truth table for read/write. 4. when a write cycle is detected, all i/os are tri-stated, even during byte writes. 5. the dqs and dqp x pins are controlled by the current cycle and the oe signal. oe is asynchronous and is not sampled with the clock. 6. cen = h, inserts wait states. 7. device will power-up deselected and the i/os in a tri-state condition, regardless of oe . 8. oe is asynchronous and is not sampled with the clock rise. it is masked internally during write cycles. during a read cycle dqs a nd dqp x = tri-state when oe is inactive or when the device is deselected, and dqs and dqp x = data when oe is active.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 11 of 28 ieee 1149.1 serial boundary scan (jtag) the cy7c1461av25/CY7C1463AV25/cy7c1465av25 incor- porates a serial boundary scan test access port (tap). this part is fully compliant with 1149.1. the tap operates using jedec-standard 2.5v/1.8v i/o logic level. the cy7c1461av25/CY7C1463AV25/cy7c1465av25 contains a tap controller, instruction register, boundary scan register, bypass register, and id register. disabling the jtag feature it is possible to operate the sram without using the jtag feature. to disable the tap controller, tck must be tied low (v ss ) to prevent clocking of the device. tdi and tms are inter- nally pulled up and may be unconnected. they may alternately be connected to v dd through a pull-up resistor. tdo should be left unconnected. upon power-up, the device will come up in a reset state which will not interfere with the operation of the device. note: 9. table only lists a partial listing of the by te write combinations. any combination of bw x is valid appropriate write will be done based on which byte write is active. truth table for read/write [2, 3, 9] function (cy7c1461av25) we bw a bw b bw c bw d read hxxxx write no bytes written lhhhh write byte a ? (dq a and dqp a ) l lhhh write byte b ? (dq b and dqp b )lhlhh write byte c ? (dq c and dqp c )lhhlh write byte d ? (dq d and dqp d ) lhhhl write all bytes lllll truth table for read/write [2, 3, 9] function (CY7C1463AV25) we bw b bw a read h x x write ? no bytes written l h h write byte a ? (dq a and dqp a )lhl write byte b ? (dq b and dqp b )llh write both bytes l l l truth table for read/write [2, 3, 9] function (cy7c1465av25) we bw x read hx write ? no bytes written l h write byte x ? (dq x and dqp x) ll write all bytes l all bw = l
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 12 of 28 tap controller state diagram the 0/1 next to each state repr esents the value of tms at the rising edge of tck. test access port (tap) test clock (tck) the test clock is used only with the tap controller. all inputs are captured on the rising edge of tck. all outputs are driven from the falling edge of tck. test mode select (tms) the tms input is used to give commands to the tap controller and is sampled on the rising edge of tck. it is allowable to leave this ball unconnected if the tap is not used. the ball is pulled up internally, resulting in a logic high level. test data-in (tdi) the tdi ball is used to serially input information into the registers and can be connected to the input of any of the registers. the register between tdi and tdo is chosen by the instruction that is loaded into the tap instruction register. tdi is internally pulled up and can be unconnected if the tap is unused in an application. tdi is connected to the most signif- icant bit (msb) of any register. (see tap controller block diagram.) test data-out (tdo) the tdo output ball is used to serially clock data-out from the registers. the output is ac tive depending upon the current state of the tap state machi ne. the output changes on the falling edge of tck. tdo is connected to the least significant bit (lsb) of any register. (see tap controller state diagram.) tap controller block diagram performing a tap reset a reset is performed by forcing tms high (v dd ) for five rising edges of tck. this reset does not affect the operation of the sram and may be performed while the sram is operating. at power-up, the tap is reset internally to ensure that tdo comes up in a high-z state. tap registers registers are connected between the tdi and tdo balls and allow data to be scanned into and out of the sram test circuitry. only one register can be selected at a time through the instruction register. data is serially loaded into the tdi ball on the rising edge of tck. data is output on the tdo ball on the falling edge of tck. instruction register three-bit instructions can be seri ally loaded into the instruction register. this register is loaded when it is placed between the tdi and tdo balls as shown in the tap controller block diagram. upon power-up, the instruction register is loaded with the idcode instruction. it is also loaded with the idcode instruction if the controller is placed in a reset state as described in the previous section. when the tap controller is in the capture-ir state, the two least significant bits are loaded with a binary ?01? pattern to allow for fault isolation of the boa rd-level serial test data path. bypass register to save time when serially shifting data through registers, it is sometimes advantageous to skip certain chips. the bypass register is a single-bit register that can be placed between the tdi and tdo balls. this allows data to be shifted through the sram with minimal delay. the bypass register is set low (v ss ) when the bypass instruction is executed. boundary scan register the boundary scan register is connected to all the input and bidirectional balls on the sr am. the length of the boundary scan register for the sram in different packages is listed in the scan register sizes table. test-logic reset run-test/ idle select dr-scan select ir-scan capture-dr shift-dr capture-ir shift-ir exit1-dr pause-dr exit1-ir pause-ir exit2-dr update-dr exit2-ir update-ir 1 1 1 0 1 1 0 0 1 1 1 0 0 0 0 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1 0 bypass register 0 instruction register 0 1 2 identification register 0 1 2 29 30 31 . . . boundary scan register 0 1 2 . . x . . . s election circuitr y selection circuitry tck t ms tap controller tdi td o
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 13 of 28 the boundary scan register is lo aded with the contents of the ram i/o ring when the tap controller is in the capture-dr state and is then placed between the tdi and tdo balls when the controller is moved to the shift-dr state. the extest, sample/preload and sample z instructions can be used to capture the contents of the i/o ring. the boundary scan order tables show the order in which the bits are connected. each bit corresponds to one of the bumps on the sram package. the msb of the register is connected to tdi, and the lsb is connected to tdo. identification (id) register the id register is loaded with a vendor-specific, 32-bit code during the capture-dr state when the idcode command is loaded in the instruction regi ster. the idcode is hardwired into the sram and can be shifted out when the tap controller is in the shift-dr state. the id register has a vendor code and other information described in the identification register definitions table. tap instruction set overview eight different instructions are possible with the three bit instruction register. all combinations are listed in the instruction codes table. three of these instructions are listed as reserved and should not be used. the other five instruc- tions are described in detail below. instructions are loaded into the tap controller during the shift-ir state when the instruction register is placed between tdi and tdo. during this state, instructions are shifted through the instruction register through the tdi and tdo balls. to execute the instruction once it is shifted in, the tap controller needs to be moved into the update-ir state. idcode the idcode instruction causes a vendor-specific, 32-bit code to be loaded into the instruction register. it also places the instruction register between the tdi and tdo balls and allows the idcode to be shifted out of the device when the tap controller enters the shift-dr state. the idcode instruction is loade d into the instruction register upon power-up or whenever the tap controller is given a test logic reset state. sample z the sample z instruction caus es the boundary scan register to be connected between the tdi and tdo pins when the tap controller is in a shift-dr state. the sample z command puts the output bus into a high-z state until the next command is given during the ?update ir? state. sample/preload sample/preload is a 1149.1 mandatory instruction. when the sample/preload instructions are loaded into the in- struction register and the tap controller is in the capture-dr state, a snapshot of data on the inputs and output pins is cap- tured in the boundary scan register. the user must be aware that th e tap controller clock can only operate at a frequency up to 20 mhz, while the sram clock operates more than an order of magnitude faster. because there is a large difference in the clock frequencies, it is possi- ble that during the capture-dr state, an input or output will undergo a transition. the tap may then try to capture a signal while in transition (metastable state). this will not harm the device, but there is no guarantee as to the value that will be captured. repeatable results may not be possible. to guarantee that the boundary scan register will capture the correct value of a signal, the sram signal must be stabilized long enough to meet the tap controller's capture set-up plus hold times (t cs and t ch ). the sram clock input might not be captured correctly if there is no way in a design to stop (or slow) the clock during a sample/p reload instruction. if this is an issue, it is still possible to capture all other signals and simply ignore the value of the ck and ck captured in the boundary scan register. once the data is captured, it is possible to shift out the data by putting the tap into the shift-dr state. this places the boundary scan register between the tdi and tdo pins. preload allows an initial data pattern to be placed at the latched parallel outputs of the boundary scan register cells prior to the selection of another boundary scan test operation. the shifting of data for the sample and preload phases can occur concurrently when required?that is, while data captured is shifted out, the pr eloaded data can be shifted in. bypass when the bypass instruction is loaded in t he instruction register and the tap is placed in a shift-dr state, the bypass register is placed between the tdi and tdo pins. the advantage of the bypass instructio n is that it shortens the boundary scan path when multiple devices are connected together on a board. extest the extest instruction enables the preloaded data to be driven out through the system out put pins. this instruction also selects the boundary scan register to be connected for serial access between the tdi and tdo in the shift-dr controller state. extest output bus tri-state ieee standard 1149.1 mandates that t he tap controller be able to put the output bus into a tri-state mode. the boundary scan register has a special bit located at bit #89 (for 165-fbga package) or bit #138 (for 209 bga package). when this scan cell, called the ?extest output bus tri-state?, is latched into the preload register during the ?update-dr? state in the tap controller, it will directly control the state of the output (q-bus) pins, when the extest is entered as the current instruction. when high, it will enable the output buffers to drive the output bus. when low, this bit will place the output bus into a high-z condition. this bit can be set by entering the sample/preload or extest command, and then shifting the desired bit into that cell, during the ?shift-dr? stat e. during ?update-dr?, the value loaded into that shift-register cell will latch into the preload register. when the extest instru ction is entered, this bit will directly control the output q-bu s pins. note that this bit is pre-set high to enable the output when the device is powered-up, and also when the tap controller is in the ?test-logic-reset? state. reserved these instructions are not im plemented but are reserved for future use. do not use these instructions.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 14 of 28 tap timing t tl test clock (tck) 123456 t est mode select (tms) t th test data-out (tdo) t cyc test data-in (tdi) t tmsh t tmss t tdih t tdis t tdox t tdov don?t care undefined tap ac switching characteristics over the operating range [10, 11] parameter description min. max. unit clock t tcyc tck clock cycle time 50 ns t tf tck clock frequency 20 mhz t th tck clock high time 25 ns t tl tck clock low time 25 ns output times t tdov tck clock low to tdo valid 5 ns t tdox tck clock low to tdo invalid 0 ns set-up times t tmss tms set-up to tck clock rise 5 ns t tdis tdi set-up to tck clock rise 5 ns t cs capture set-up to tck rise 5 ns hold times t tmsh tms hold after tck clock rise 5 ns t tdih tdi hold after clock rise 5 ns t ch capture hold after clock rise 5 ns notes: 10.t cs and t ch refer to the set-up and hold time requirements of latching data from the boundary scan register. 11.test conditions are specified using the load in tap ac test conditions. t r /t f = 1 ns.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 15 of 28 1.8v tap ac test conditions input pulse levels ............ ........................ 0.2v to v ddq ? 0.2 input rise and fall time ........... ..........................................1 ns input timing referenc e levels........................................... 0.9v output reference levels .................................................. 0.9v test load termination supply vo ltage .............................. 0.9v 1.8v tap ac output load equivalent 2.5v tap ac test conditions input pulse levels ................................................ v ss to 2.5v input rise and fall time ..................................................... 1 ns input timing reference levels ... ......................................1.25v output reference levels ........... ......................................1.25v test load termination supply voltage .............................1.25v 2.5v tap ac output load equivalent note: 12. all voltages referenced to v ss (gnd). t do 0.9v 20p f z = 50 ? o 50 ? t do 1.25v 20p f z = 50 ? o 50 ? tap dc electrical characteristics and operating conditions (0c < ta < +70c; vdd = 2.375 to 2.625 unless otherwise noted) [12] parameter description test conditions min. max. unit v oh1 output high voltage i oh = -1.0 ma, v ddq = 2.5v 2.0 v v oh2 output high voltage i oh = -100 a v ddq = 2.5v 2.1 v v ddq = 1.8v 1.6 v v ol1 output low voltage i ol =1.0 ma v ddq = 2.5v 0.4 v v ol2 output low voltage i ol = 100 a v ddq = 2.5v 0.2 v v ddq = 1.8v 0.2 v v ih input high voltage v ddq = 2.5v 1.7 v dd + 0.3 v v ddq = 1.8v 1.26 v dd + 0.3 v v il input low voltage v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current gnd < v in < v ddq ?5 5 a identification register definitions instruction field cy7c1461av25 (1 mbit 36) CY7C1463AV25 (2 mbit 18) cy7c1465av25 (512k 72) description revision number (31:29) 000 000 000 describes the version number device depth (28:24) 01011 01011 01011 reserved for internal use architecture/memory type (23:18) 001001 001001 001001 defines memory type and archi- tecture bus width/density(17:12) 100111 010111 110111 defines width and density cypress jedec id code (11:1) 00000110100 0000011010 0 00000110100 allows uni que identification of sram vendor id register presence indicator (0) 1 1 1 indicates the presence of an id register
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 16 of 28 scan register sizes register name bit size ( 36) bit size ( 18) bit size ( 72) instruction 33 3 bypass 11 1 id 32 32 32 boundary scan order-165fbga 89 89 ? boundary scan order- 209bga ?? 138 identification codes instruction code description extest 000 captures i/o ring contents. places the boundary scan register between tdi and tdo. forces all sram outputs to high-z state. idcode 001 loads the id register with the vendor id code and places the register between tdi and tdo. this operation does not affect sram operations. sample z 010 captures i/o ring contents. plac es the boundary scan register between tdi and tdo. forces all sram output drivers to a high-z state. reserved 011 do not use: this instruct ion is reserved for future use. sample/preload 100 captures i/o ring contents. pl aces the boundary scan regi ster between tdi and tdo. does not affect sram operation. reserved 101 do not use: this instruct ion is reserved for future use. reserved 110 do not use: this instruct ion is reserved for future use. bypass 111 places the bypass register between tdi and tdo. this operation does not affect sram operations. 165-ball fbga boundary scan order [13] cy7c1461av25 (1 mbit 36) cy7c1461av25 (1 mbit 36) bit# ball id bit# ball id bit# ball id 1n642 a7 83 p2 2n743 b7 84 r4 3 n10 44 b6 85 p4 4 p11 45 a6 86 n5 5p846 b5 87 p6 6r847 a5 88 r6 7 r9 48 a4 89 internal 8p949 b4 CY7C1463AV25 (2 mbit 18) 9p1050 b3 10 r10 51 a3 1 n6 11 r11 52 a2 2 n7 12 h11 53 b2 3 10n 13 n11 54 c2 4 p11 14 m11 55 b1 5 p8 15 l11 56 a1 6 r8 16 k11 57 c1 7 r9 17 j11 58 d1 8 p9 18 m10 59 e1 9 p10 19 l10 60 f1 10 r10 note: 13. bit# 89 is preset high.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 17 of 28 20 k10 61 g1 11 r11 21 j10 62 d2 12 h11 22 h9 63 e2 13 n11 23 h10 64 f2 14 m11 24 g11 65 g2 15 l11 25 f11 66 h1 16 k11 26 e11 67 h3 17 j11 27 d11 68 j1 18 m10 28 g10 69 k1 19 l10 29 f10 70 l1 20 k10 30 e10 71 m1 21 j10 31 d10 72 j2 22 h9 32 c11 73 k2 23 h10 33 a11 74 l2 24 g11 34 b11 75 m2 25 f11 35 a10 76 n1 26 e11 36 b10 77 n2 27 d11 37 a9 78 p1 28 g10 38 b9 79 r1 29 f10 39 c10 80 r2 30 e10 40 a8 81 p3 31 d10 41 b8 82 r3 32 c11 165-ball fbga boundary scan order (continued) [13] cy7c1461av25 (1 mbit 36) cy7c1461av25 (1 mbit 36) bit# ball id bit# ball id bit# ball id 165-ball fbga boundary scan order [13] CY7C1463AV25 (2 mbit 18) bit# ball id bit# ball id 33 a11 61 g1 34 b11 62 d2 35 a10 63 e2 36 b10 64 f2 37 a9 65 g2 38 b9 66 h1 39 c10 67 h3 40 a8 68 j1 41 b8 69 k1 42 a7 70 l1 43 b7 71 m1 44 b6 72 j2 45 a6 73 k2 46 b5 74 l2 47 a5 75 m2 48 a4 76 n1 49 b4 77 n2 50 b3 78 p1 51 a3 79 r1 52 a2 80 r2 53 b2 81 p3 54 c2 82 r3 55 b1 83 p2 56 a1 84 r4 57 c1 85 p4 58 d1 86 n5 59 e1 87 p6 60 f1 88 r6 89 internal 165-ball fbga boundary scan order (continued) [13] CY7C1463AV25 (2 mbit 18) bit# ball id bit# ball id
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 18 of 28 209-ball bga boundary scan order [13, 14] cy7c1465v25 (512k x 72) cy7c1465v25 (512k x 72) bit# ball id bit# ball id bit# ball id bit# ball id 1w635 j6 69 d6 104k1 2v636 f6 70 g6 105n6 3u637 k8 71 h6 106k3 4w738 k9 72 c6 107k4 5 v7 39 k10 73 b6 108 k6 6 u7 40 j11 74 a6 109 k2 7 t7 41 j10 75 a5 110 l2 8v842 h11 76 b5 111l1 9u843 h10 77 c5 112m2 10 t8 44 g11 78 d5 113 m1 11 v9 45 g10 79 d4 114 n2 12 u9 46 f11 80 c4 115 n1 13 p6 47 f10 81 a4 116 p2 14 w11 48 e10 82 b4 117 p1 15 w10 49 e11 83 c3 118 r2 16 v11 50 d11 84 b3 119 r1 17 v10 51 d10 85 a3 120 t2 18 u11 52 c11 86 a2 121 t1 19 u10 53 c10 87 a1 122 u2 20 t11 54 b11 88 b2 123 u1 21 t10 55 b10 89 b1 124 v2 22 r11 56 a11 90 c2 125 v1 23 r10 57 a10 91 c1 126 w2 24 p11 58 c9 92 d2 127 w1 25 p10 59 b9 93 d1 128 t6 26 n11 60 a9 94 e1 129 u3 27 n10 61 d8 95 e2 130 v3 28 m11 62 c8 96 f2 131 t4 29 m10 63 b8 97 f1 132 t5 30 l11 64 a8 98 g1 133 u4 31 l10 65 d7 99 g2 134 v4 32 k11 66 c7 100 h2 135 w5 33 m6 67 b7 101 h1 136 v5 34 l6 68 a7 102 j2 137 u5 103 j1 138 internal note: 14. bit# 138 is preset high.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 19 of 28 maximum ratings (above which the useful life may be impaired. for user guide- lines, not tested.) storage temperature .............. .............. ..... ?65c to +150c ambient temperature with power applied ........... .............. .............. ..... ?55c to +125c supply voltage on v dd relative to gnd ........?0.5v to +4.6v dc voltage applied to outputs in tri-state ...........................................?0.5v to v ddq + 0.5v dc input voltage ................................... ?0.5v to v dd + 0.5v current into outputs (low) .... .....................................20 ma static discharge voltage ......... ........... ............ .......... >2001v (per mil-std-883, method 3015) latch-up current .................................................... >200 ma operating range range ambient temperature v dd v ddq commercial 0c to +70c 2.5v ?5%/+5% 1.7v to v dd electrical characteristics over the operating range [14, 15] parameter description test conditions min. max. unit v dd power supply voltage 2.375 2.625 v v ddq i/o supply voltage v ddq = 2.5v 2.375 v dd v v ddq = 1.8v 1.7 1.9 v v oh output high voltage v dd = min., i oh = ? 1.0 ma, v ddq = 2.5v 2.0 v v dd = min., i oh = ?100 a, v ddq = 1.8v 1.6 v v ol output low voltage v dd = max., i ol = 1.0 ma, v ddq = 2.5v 0.4 v v dd = max., i ol = 100 a, v ddq = 1.8v 0.2 v v ih input high voltage [14] v ddq = 2.5v 1.7 v dd + 0.3v v v ddq = 1.8v 1.26 v dd + 0.3v v v il input low voltage [14] v ddq = 2.5v ?0.3 0.7 v v ddq = 1.8v ?0.3 0.36 v i x input load current except zz and mode gnd v i v ddq ?5 5 a input current of mode input = v ss ?5 a input = v dd 30 a input current of zz input = v ss ?30 a input = v dd 5 a i oz output leakage current gnd v i v ddq, output disabled ?5 5 a i dd v dd operating supply current v dd = max., i out = 0 ma, f = f max = 1/t cyc 7.5-ns cycle, 133 mhz 270 ma 10-ns cycle, 100 mhz 250 ma i sb1 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v ih or v in v il f = f max , inputs switching 7.5-ns cycle, 133 mhz 150 ma 10-ns cycle, 100 mhz 150 ma i sb2 automatic ce power-down current?cmos inputs v dd = max, device deselected, v in 0.3v or v in > v dd ? 0.3v, f = 0, inputs static all speeds 100 ma i sb3 automatic ce power-down current?cmos inputs v dd = max, device deselected, or v in 0.3v or v in > v ddq ? 0.3v f = f max , inputs switching 7.5-ns cycle, 133 mhz 150 ma 10-ns cycle, 100 mhz 150 ma i sb4 automatic ce power-down current?ttl inputs v dd = max, device deselected, v in v dd ? 0.3v or v in 0.3v, f = 0, inputs static all speeds 110 ma shaded areas contain advance information. notes: 14. overshoot: v ih (ac) < v dd +1.5v (pulse width less than t cyc /2), undershoot: v il (ac) > ?2v (pulse width less than t cyc /2). 15. t power-up : assumes a linear ramp from 0v to v dd (min.) within 200 ms. during this time v ih < v dd and v ddq < v dd .
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 20 of 28 thermal resistance [15] parameter description test conditions 100 tqfp 165 fbga 209 fbga unit ja thermal resistance (junction to ambient) test conditions follow standard test methods and procedures for measuring thermal impedance, per eia / jesd51. 25.21 20.8 25.31 c/w jc thermal resistance (junction to case) 2.28 3.2 4.48 c/w capacitance [15] parameter description test conditions 100 tqfp 165 fbga 209 fbga unit c in input capacitance t a = 25c, f = 1 mhz, v dd = 2.5v v ddq = 2.5v 6.5 5 5 pf c clk clock input capacitance 3 5 5 pf c i/o input/output capacitance 5.5 7 7 pf ac test loads and waveforms switching characteristics over the operating range [20, 21] parameter description 133 mhz 100 mhz unit min. max. min. max. t power [16] 1 1 ms clock t cyc clock cycle time 7.5 10 ns t ch clock high 2.5 3.0 ns t cl clock low 2.5 3.0 ns output times t cdv data output valid after clk rise 6.5 8.5 ns t doh data output hold after clk rise 2.5 2.5 ns t clz clock to low-z [17, 18, 19] 2.5 2.5 ns shaded areas contain advance information. notes: 15. tested initially and after any design or process change that may affect these parameters. 16. this part has a voltage regulator internally; t power is the time that the power needs to be supplied above v dd (minimum) initially, before a read or write operation can be initiated. 17. t chz , t clz ,t oelz , and t oehz are specified with ac test conditions shown in (b) of ac test loads. transition is measured 200 mv from steady-state voltage . 18. at any given voltage and temperature, t oehz is less than t oelz and t chz is less than t clz to eliminate bus contention between srams when sharing the same data bus. these specifications do not imply a bus contention condition, but reflect para meters guaranteed over worst case user conditions. device is designed to achieve high-z prior to low-z under the same system conditions 19. this parameter is sampled and not 100% tested. 20. timing reference level is 1.25v when v ddq = 2.5v and is 0.9v when v ddq = 1.8v. 21. test conditions shown in (a) of ac test loads unless otherwise noted. output r = 1667 ? r = 1538 ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 1.25v 2.5v all input pulses v ddq gnd 90% 10% 90% 10% 1ns 1ns (c) 2.5v i/o test load output r = 14k ? r = 14k ? 5pf including jig and scope (a) (b) output r l = 50 ? z 0 = 50 ? v t = 0.9v 1.8v all input pulses v ddq - 0.2 0.2 90% 10% 90% 10% 1ns 1ns (c) 1.8v i/o test load
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 21 of 28 t chz clock to high-z [17, 18, 19] 3.8 0 4.5 ns t oev oe low to output valid 3.0 3.8 ns t oelz oe low to output low-z [17, 18, 19] 0 0 ns t oehz oe high to output high-z [17, 18, 19] 3.0 4.0 ns set-up times t as address set-up before clk rise 1.5 1.5 ns t als adv/ld set-up before clk rise 1.5 1.5 ns t wes we , bw x set-up before clk rise 1.5 1.5 ns t cens cen set-up before clk rise 1.5 1.5 ns t ds data input set-up before clk rise 1.5 1.5 ns t ces chip enable set-up before clk rise 1.5 1.5 ns hold times t ah address hold after clk rise 0.5 0.5 ns t alh adv/ld hold after clk rise 0.5 0.5 ns t weh we , bw x hold after clk rise 0.5 0.5 ns t cenh cen hold after clk rise 0.5 0.5 ns t dh data input hold after clk rise 0.5 0.5 ns t ceh chip enable hold after clk rise 0.5 0.5 ns switching characteristics over the operatin g range (continued) [20, 21] parameter description 133 mhz 100 mhz unit min. max. min. max.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 22 of 28 switching waveforms read/write waveforms [22, 23, 24] notes: 22. for this waveform zz is tied low. 23. when ce is low, ce 1 is low, ce 2 is high and ce 3 is low. when ce is high, ce 1 is high or ce 2 is low or ce 3 is high. 24. order of the burst sequence is determined by the status of th e mode (0 = linear, 1 = interleaved). burst operations are opti onal. write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 23 of 28 nop, stall and deselect cycles [22, 23, 25] note: 25. the ignore clock edge or stall cycle (clock 3) illustrates cen being used to create a pause. a write is not performed during this cycle. switching waveforms (continued) write d(a1) 123 456789 clk t cyc t cl t ch 10 ce t ceh t ces we cen t cenh t cens bw x adv/ld t ah t as address a1 a2 a3 a4 a5 a6 a7 t dh t ds dq c ommand t clz d(a1) d(a2) q(a4) q(a3) d(a2+1) t doh t chz t cdv write d(a2) burst write d(a2+1) read q(a3) read q(a4) burst read q(a4+1) write d(a5) read q(a6) write d(a7) deselect oe t oev t oelz t oehz don?t care undefined d(a5) t doh q(a4+1) d(a7) q(a6)
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 24 of 28 zz mode timing [26, 27] switching waveforms (continued) t zz i supply clk zz t zzrec a ll inputs (except zz) don?t care i ddzz t zzi t rzzi outputs (q) high-z deselect or read only ordering information speed (mhz) ordering code package name part and package type operating range 133 cy7c1461av25-133axc a101 lead-free 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables CY7C1463AV25-133axc cy7c1461av25-133bzc bb165c 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) CY7C1463AV25-133bzc cy7c1465av25-133bgc bb209a 209-ball ball grid array (14 22 1.76 mm) cy7c1461av25-133bzxc bb165c lead-free 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) CY7C1463AV25-133bzxc cy7c1465av25-133bgxc bb209a lead-free 209-ball ball grid array (14 22 1.76 mm) 100 cy7c1461av25-100axc CY7C1463AV25-100axc a101 100-lead thin quad flat pack (14 x 20 x 1.4mm) 3 chip enables cy7c1461av25-100bzc bb165c 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) CY7C1463AV25-100bzc cy7c1465av25-100bgc bb209a 209-ball ball grid array (14 22 1.76 mm) cy7c1461av25-100bzxc bb165c lead-free 165-ball fine pitch ball grid array (15 x 17 x 1.4 mm) CY7C1463AV25-100bzxc cy7c1465av25-100bgxc bb209a lead-free 209-ball ball grid array (14 22 1.76 mm) shaded areas contain advance information. notes: 26. device must be deselected when entering zz mode. see truth ta ble for all possible signal conditions to deselect the device. 27. dqs are in high-z when exiting zz sleep mode.
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 25 of 28 package diagrams 51-85050-a 100-pin thin plastic quad flatpack (14 x 20 x 1.4 mm) a101 51-85050-*a
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 26 of 28 package diagrams (continued) a 1 pin 1 corner 17.000.10 15.000.10 7.00 1.00 ?0.450.05(165x) ?0.25 m c a b ?0.05 m c b a 0.15(4x) 0.35 1.40 max. seating plane 0.530.05 0.25 c 0.15 c pin 1 corner top view bottom view 2 3 4 5 6 7 8 9 10 10.00 14.00 b c d e f g h j k l m n 11 11 10 9 8 67 5 4 3 2 1 p r p r k m n l j h g f e d c b a c 1.00 5.00 0.36 +0.05 -0.10 165-ball fbga (15 x 17 x 1.40 mm) bb165c 51-85165-*a
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 27 of 28 ? cypress semiconductor corporation, 2005. the information contained herein is subject to change without notice. cypress semic onductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress product. nor does it convey or imply any license under patent or ot her rights. cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agr eement with cypress. furthermore, cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to re sult in significant injury to the user. the inclusion of cypress products in life-support systems application implies that the manu facturer assumes all risk of such use and in doing so indemni fies cypress against all charges. nobl and no bus latency are trademarks of cypress semiconduc tor corporation. zbt is a trademark of integrated device technologies. all product and company names mentioned in this document are the trademarks of their respective holders. package diagrams (continued) 209-ball fbga (14 x 22 x 1.76 mm) bb209a 51-85167-**
preliminary cy7c1461av25 CY7C1463AV25 cy7c1465av25 document #: 38-05355 rev. *b page 28 of 28 document history page document title: cy7c1461av25/CY7C1463AV25/cy7c1465av25 36-mbit (1m x 36/2m x 18/512k x 72) flow-through sram with nobl? architecture document number: 38-05355 rev. ecn no. issue date orig. of change description of change ** 254911 see ecn syt new data sheet changed part number from previous revi sion. new and old part number differ by the letter ?a.? *a 300131 see ecn syt removed 150- and 177-mhz speed bins changed ja and jc from tbd to 25.21 and 2.58 c/w, respectively, for tqfp package added lead-free information for 100-pin tqfp, 165 fbga and 209 bga packages added ?lead-free bg and bz packages availability? below the ordering infor- mation *b 320813 see ecn syt changed h9 pin from v ssq to v ss on the pin configuration table for 209 fbga changed the test condition from v dd = min. to v dd = max for v ol in the electrical characteristics table. replaced the tbd?s for i dd , i sb1 , i sb2 , i sb3 and i sb4 to their respective values. replaced tbd?s for ja and jc to their respective values for 165 fbga and 209 fbga packages on the thermal resistance table. changed c in , c clk and c i/o to 6.5, 3 and 5.5 pf from 5, 5 and 7 pf for tqfp package. removed ?lead-free bg and bz package s availability? comment below the ordering information

▲Up To Search▲

Price & Availability of CY7C1463AV25

	To Download CY7C1463AV25 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .